1. Field of the Invention
This invention relates to a polishing method. More particularly, it relates to a polishing method that is employed when polycrystalline silicon is ground in such a manner as to bury it into an isolation groove during a flattening step of an isolation insulating film in a fabrication process of a semiconductor device.
2. Description of the Related Art
Recently, a polishing method using a polishing solution has been employed to make flat an isolating insulation film isolating semiconductor devices, or to make flat an inter-level insulating film of a multilayered wiring.
A polishing solution used at the fabrication stage of conventional semiconductor devices is directed to polishing silicon single crystal and is not suitable for polishing an insulating film such as a silicon dioxide film. The conventional polishing solution uses an alkali solution prepared by dissolving an organic compound, and it cannot therefore provide a sufficient polishing rate for insulators. Accordingly, attempts have been made to improve the polishing rate by increasing the concentration of a grain such as colloidal silica or increasing the pressure at the time of polishing, but it has been difficult to significantly improve the polishing rate.
FIG. 1 of the accompanying drawings shows a polishing rate when a SiO.sub.2 film is ground by using a commercially available polishing solution ("Nalco 2350", a product of Nalco Kabushiki Kaisha) prepared by mixing colloidal silica in an alkali solution dissolving therein an organic compound with a pressure of 400 g/cm.sup.2 and with a polishing pad commercially available as "Rodel SUBA 500" (a product of Rodel Kabushiki Kaisha). When the concentration of colloidal silica is low, the polishing rate is about 0.2 .mu.m/hr and even when the concentration of colloidal silica is increased, the polishing rate is only about 0.7 .mu.m/hr.
Moreover, when the concentration of the colloidal silica grain is increased, the feed of the grain cannot be made uniform to the entire surface of a wafer, so that the polishing quantity obtained is different depending upon the position, thereby rendering the polishing non-uniform.
When the polishing solution is adjusted to a high alkali range of a pH of at least 12 and is used for polishing, the polishing rate can be improved, but other problems develop. Namely, the colloidal silica as the grain is dissolved in such a high alkali region, the composition of the polishing solution changes and thus, the polishing rate fluctuates thereby resulting in nonuniform polishing.
As described above, the polishing solution for the silicon single crystal has a drawback in that its polishing rate is low. If the concentration of the grain is increased so as to improve the polishing rate, polishing becomes non-uniforms, and if polishing is carried out by adjusting the polishing solution to a high alkali range, the grain is dissolved to change the composition of the polishing solution, and uniform polishing cannot be accomplished.
In an isolation structure for isolating an element by an isolation groove in a semiconductor device, on the other hand, an isolating insulation film is formed on the inner wall of the isolation groove, and polycrystalline silicon is buried into the isolation groove. A polishing technique that so effects the polishing as to leave polycrystalline silicon in the isolation groove, for burying the polycrystalline silicon in the isolation groove, has drawn increasing attention.
The polishing solution filed in the patent application by the same Applicant as the present invention is known as a polishing solution for polishing such a polycrystalline silicon (KOKAI (Japanese Unexamined Patent Publication) No. 2-146732). This polishing solution is prepared by adding colloidal silica to an aqueous solution of ethylenediamine or hydrazine.
The polishing method using this polishing solution will be explained with reference to FIG. 2.
An isolation groove 2 is formed in a silicon substrate 1 by ordinary photolithography and subsequently, a 0.1 to 0.2 .mu.m-thick SiO.sub.2 film 3 is formed on the silicon substrate 1 inclusive of the inner surface of the isolation groove 2 by thermal oxidation (FIG. 2(a)). This SiO.sub.2 film 3 serves as a isolating insulation film 3A inside the isolation ditch 2 and as a polishing stopper film 3B on the upper surface of the silicon substrate 1.
Next, a 1.5 .mu.m-thick non-doped polycrystalline silicon layer 4 that sufficiently fills the inside of the isolation groove 2 and the upper surface of which is flattened is formed on the silicon substrate 1 by CVD (chemical vapor deposition; FIG. 1(b)).
The upper surface of the polycrystalline silicon layer 4 is polished chemically and mechanically using a surface grinder having an abrasive cloth bonded thereto while the polishing solution described above is added drop-wise. A silicon hydrate film 6 having a thickness of dozens of nm is formed on the surface of the polycrystalline silicon layer 4 due to the action of ethylenediamine or hydrazine, and this silicon hydrate film 6 is peeled by abrasion by the colloidal silica. The exposed surface of the polycrystalline silicon layer 4 changes to the silicon hydrate film 6 by the action of ethylenediamine or hydrazine, and this silicon hydrate film 6 is peeled because of the friction of the colloidal silica. In this way, polishing proceeds (FIG. 2(c)).
As polishing proceeds and the SiO.sub.2 film 3 functioning as the polishing stopper film 3B is exposed, polishing does not proceed around the isolation groove 2, so that over-polishing is effected and an isolation structure having the polycrystalline silicon layer 4 buried into the separation ditch 2 is formed (FIG. 2(d)).
However, when the polycrystalline silicon layer 4 is polished by using the conventional polishing solution, the polishing residues of the polycrystalline silicon layer 4 or so-called "poly-protuberances" 8 are left in some cases on the surface of the polishing stopper film 3B of the silicon substrate 1. If the polyprotuberances are left in the active region, they result in a window opening defect in a subsequent step and eventually, in the formation of a defective chip, which results in abnormal semiconductor devices, and a drop in production yield.